Challenge Page Registration

Bharat AI-SoC Student Challenge

A project-based virtual challenge to ignite innovation in AI-driven System-on-Chip (SoC) design.

Mode Virtual Project Challenge

Team Size 1–3 Students

Eligibility Indian Institutes Only

Notice: We are pleased to announce the winning teams under each problem statement. Following a rigorous evaluation process, the winning teams have demonstrated exceptional innovation and execution. Congratulations to all the winners on this achievement. Further details will be shared via email.

View each problem statement below for the winning team details.

Registration Closed

The registration period for the Bharat AI-SoC Student Challenge has ended.

Objective

Enhance industry-relevant skills through project-based learning in the space of AI and SoC via an experiential mini-project.

To ignite a culture of innovation by empowering students to ideate next-generation SoC solutions that unite AI and sustainability, leveraging Arm architecture — preparing them to shape the semiconductor future.

Eligibility Criteria

Participants must be Indian nationals.
Participants must be associated with an Indian institute.
Students must be nominated by their respective college.
Teams of 1–3 students can apply.
All team members must be from the same college.
Team must have a Team Leader & Faculty Mentor.
Participants must be willing to learn about Edge AI, Software-Hardware Co-design, and Embedded Systems.

Challenge Guidelines & Terms

Only eligible students can participate.
Team size: 1–3 members.
Only Team Leader registers for the team.
Duplicate registration results in rejection.
Registration details must be accurate.
Mentoring by industry & academic experts (virtual) & college mentors (local).
Teams can reach out to mentors(experts) via support email id as mentioned.
Mini project to be hosted on GitHub and submitted using the challenge submission form.
All Challenge related notifications & updates will posted in this page.
Winners must provide college ID & documents.
Updates will be posted on this page.
The selection of winners will be solely at the discretion of the organizers of this challenge.
Support: support@armbharatchallenge.com

Note: Incorrect or duplicate entries may result in disqualification.

Detailed Timeline

Activity	Description	Start	End
Registration	Interested students can register using the below registration link	05 Jan 2026	20 Jan 2026
Mentoring Session	An online mentoring session by industry & academic experts will be conducted whose details will be shared in this webpage & also mailed to registrants	10 Jan 2026	20 Jan 2026
Project Submission	Project Submission form will be shared with the participants	10 Feb 2026	20 Feb 2026
Project Evaluation	The submitted projects will be evaluated by the industry & academic experts	15 Feb 2026	05 Mar 2026
Finals	Selected teams will be invited for a virtual meetup/hack to deliver a pitch	Mid of March
Winners Announcement	The winning teams will be announced in this webpage with the details of the Rewards	Last week of March

Support & Queries

For general support, email:

support@armbharatchallenge.com

For any technical queries with regards to the problem statements, please mail your queries to tech-queries@armbharatchallenge.com clearly mentioning the problem statement number in the subject line.

For get started resources:

Arm Education Resources

All updates will be posted on this page.

Frequently Asked Questions (FAQ)

Find answers to common questions about the Bharat AI-SoC Student Challenge.

Click here to view FAQs →

Finalist Announcement

The following teams have been shortlisted for the final virtual evaluation and project demonstration round. Final evaluations are scheduled between 19th and 20th March 2026.

We are pleased to announce that the following teams, under each problem statement, have been shortlisted for the final virtual evaluation round. The next stage will include a virtual evaluation and project demonstration, scheduled between 19th and 20th March 2026. Finalists are requested to stay prepared and look out for further communication via email with detailed instructions. Kindly refer to the table below for the details of the shortlisted finalist teams under each problem statement. Congratulations once again, and we wish you all the very best for the final online demonstration.

PS 1 Offline, Privacy-Preserving Hindi Voice Assistant on Raspberry Pi

SL	Institution	Team Lead	Member 2	Member 3	Mentor
1	Shri Vaishnav Vidyapeeth Vishwavidyalaya, Indore	Nikhil Bardeja	Garvit Hindoliya	Jitendra Ahirwar	Preet Jain
2	Indian Institute of Information Technology, Bhagalpur	Vedant Singh	-	-	Dr. Dheeraj Kr. Sinha
3	Heritage Institute of Technology, Kolkata	Maulik Parasramka	Shresth Parsramka	Arka Majumder	Mousiki Kar
4	Rajalakshmi Engineering College, Thandalam	Keerthibalan G	Kadhiroliselvan R D	Levin Prince L	Dr. S Chitra
5	Indian Institute of Information Technology Vadodara	Soham Jaydeep Dhapre	Vishesh Sethiya	Shrishti Singh	Dr. Bhupendra Kumar
6	Jaypee Institute of Information Technology, Noida	Pushkar Chaturvedi	Rishab Jain	-	Mr. Ajay Kumar

PS 2 Touchless HCI for Media Control Using Hand Gestures on NVIDIA Jetson Nano

SL	Institution	Team Lead	Member 2	Member 3	Mentor
1	Vellore Institute of Technology, Chennai	P A Athithiya	Nukilan J	Mathesh V	Muthulakshmi S
2	Indian Institute of Technology, Roorkee	Anand Kumar	Ayush Kumar Mandal	Ishika Chikate	Dr. Tharun Kumar Reddy Bollu
3	National Institute of Technology, Surathkal	Shresh Parti	Rushil Jain	Sriprahlad Mukunthan	Dr. Sumam David
4	Jadavpur University, Kolkata	Pushpal Bhar	Arghya Pratim Biswas	Subhojit Khatua	Sheili Sinha Chaudhuri
5	Thapar Institute of Engineering & Technology, Patiala	Amitoj Singh	Shivanjay	Varun Bothra	Dr. Anu Bajaj
6	B. V. Raju Institute of Technology, Narsapur	Akalankam Pranav	Enumula Bhuvan Shekar Reddy	Bandari Govardhan	Dr. U Gnaneshwara Chary

PS 3 Real-Time Road Anomaly Detection from Dashcam Footage on Raspberry Pi

SL	Institution	Team Lead	Member 2	Member 3	Mentor
1	Indian Institute of Technology, Madras	Ram Bhatta	Ashwaat Tarun TS	Tanish Chudiwal	Pravin Nair
2	National Institute of Technology, Rourkela	Tom Mathew	Ben Biju	Shreeram Balasubramanian	Prof. Manish Okade
3	Indian Institute of Information Technology Design and Manufacturing, Kurnool	Gayatri Akula	Jyoshika	Omkara Sri Harsha	Dr. Eswaramoorthy K V
4	Amrita Vishwa Vidhyapeetham, Chennai	Janani A	Yashika R S	Hariharasudhan P	Dr. Ganesh Kumar C
5	Indian Institute of Technology, Roorkee	Agrim Bhanot	Jashanpreet Singh Ubi	Sarvagya Jain	Biplab Sarkar
6	Indian Institute of Technology, Madras	Ashvin Ganeshrao Ambatwar	Shivam Kumar	Girish Bhat	Panchavarnam Baskaran Nadar

PS 4 Real-Time On-Device Speech-to-Speech Translation Using SME2 and/or NEON on Arm CPU

SL	Institution	Team Lead	Member 2	Member 3	Mentor
1	Indian Institute of Technology, Tirupati	Pratik Raj	Meet Rana	Praval Gupta	Dr. Thiyagarajan R
2	R. V. College of Engineering, Bangalore	Kamath Abhay Sunil	Harini G Iyay	Nandana P Pillai	Dr. Uttara Kumari
3	Chennai Institute of Technology, Malayambakkam	V Paresh Kumar	Vishnu Vardhan KS	Yugawathi E	Mr. V Prem Sangeeth
4	Indian Institute of Information Technology, Design and Manufacturing, Kancheepuram	Rohan J S	-	-	Shri. Hariharan Seshadri
5	Indian Institute of Information Technology Design and Manufacturing, Kurnool	Anshu Patra	Ramakrishna Sen	Dhruv Singh	Dr. Rangababu Peesapati
6	Indian Institute of Technology, Hyderabad	Ashirbad Sahu	Animish Sharma	Divyansh Atri	Priyesh Shukla

PS 5 Real-Time Object Detection Using Hardware-Accelerated CNN on Xilinx Zynq FPGA with Arm Processor

SL	Institution	Team Lead	Member 2	Member 3	Mentor
1	SRM Easwari Engineering College, Chennai	Pervin Korino Dasan A	Gokul Siddarth K C	Naseem Fatimah A K J	Dr. S. Ashok Kumar
2	Indian Institute of Technology, Roorkee	Ketan Roy	Daksh Pandey	-	Tharun Kumar Reddy Bollu
3	Chennai Institute of Technology, Malayambakkam	Vignesh S	N A Akilan	Devaram A	Aathilakshmi S
4	Indian Institute of Technology, Jodhpur	Aayush Verma	Bharti Pareek	Sakshi Thakur	Dr Binod Kumar
5	B V Raju Institute of Technology, Narsapur	Cherala Rohan	Karthik Pakala	-	Dr. U. Gnaneshwara Chary
6	Indian Institute of Information Technology Design and Manufacturing, Kancheepuram	A Sasi Vadan	A Teja Swaroop	-	Prof. Binsu J Kailath

Project Problem Statements

Choose one of the following problem statements as a starting point for your project. Click to expand each project and view suggested objectives

Problem Statement 1 Offline, Privacy-Preserving Hindi Voice Assistant on Raspberry Pi

Winning Team

Team	Spark
Institution	Heritage Institute of Technology, Kolkata
Team Members	Maulik Parasramka, Shresth Parsramka, Arka Majumder

Objective

Develop a low-latency, privacy-preserving voice assistant on an Arm-based SBC (e.g., Raspberry Pi) that processes Hindi voice commands entirely offline. The assistant should handle local queries (time, weather, etc.) using on-device ASR and TTS.

Project Description

Students will build an embedded speech pipeline performing:

Speech-to-text using a lightweight ASR model (e.g., Coqui STT or fine-tuned wav2vec2 for Hindi).
Command parsing and intent recognition in Python.
Text-to-speech responses using local TTS (eSpeak-NG or Festival).
End-to-end on the Raspberry Pi CPU with no cloud dependency.

Key Requirements

Hardware:
- Raspberry Pi 5 or 4 (or similar Arm SBC).
- USB microphone.
- Speaker via 3.5 mm jack or HDMI.
- Where possible, aim to use the CPU without additional accelerators/hats. Solutions that are well-optimised through use of Quantisation, KleidiAI, and appropriate model selection - and therefore able to run entirely on CPU - are of great interest.
Software:
- Python with PyAudio for audio I/O.
- Coqui STT or fine-tuned wav2vec2 for ASR, or similar.
- eSpeak-NG or Festival for TTS.
- Custom Python logic for intent recognition and command execution.

Performance Targets

Sub-2-second response time per command.
Accurate recognition for 10–15 Hindi commands.
Robust, fully offline operation.

Deliverables

Source code for the full voice assistant pipeline.
Documentation of any model fine-tuning / optimization steps.
Demo video showing responses to multiple commands.
Short report on architecture, challenges in Hindi ASR/TTS, and performance metrics.

Learning Outcomes

Hands-on experience with embedded speech AI and offline ASR/TTS.
Understanding challenges of regional language processing.
Integrating ASR, simple NLP/intent logic, and TTS on a constrained platform.

Mentoring session schedule and details

PS#	Date	Time	Meeting Link
1	9th Feb	3 – 3:30 PM	Zoom link Meeting ID: 927 2420 9713 Passcode: 808049

Problem Statement 2 Touchless HCI for Media Control Using Hand Gestures on NVIDIA Jetson Nano

Winning Team

Team	Velocity Gate
Institution	National Institute of Technology, Surathkal
Team Members	Shresh Parti, Rushil Jain, Sriprahlad Mukunthan

Objective

Create a touchless HCI system using an NVIDIA Jetson Nano that translates real-time hand gestures into media control commands (e.g., play/pause, volume) for a local player such as VLC.

Project Description

Students will use MediaPipe Hands (optimized for Arm CPU and Jetson GPU) to detect hand landmarks, then classify gestures and map them to keyboard shortcuts using Python libraries like pynput or xdotool.

Key Requirements

Hardware:
- NVIDIA Jetson Nano Developer Kit.
- USB webcam.
- Monitor and standard peripherals.
Software:
- JetPack OS with CUDA support.
- Python, OpenCV, MediaPipe.
- Media player application (e.g., VLC).

Performance Targets

>90% gesture recognition accuracy in controlled lighting.
<200 ms end-to-end latency for gesture → action.
Stable at ≥15 FPS.

Deliverables

Source code for gesture recognition and control logic.
Defined gesture set and mapping table.
Demo video of real-time media control.
Report on design, model choice and performance analysis.

Learning Outcomes

Practical experience with real-time edge computer vision.
Pipeline optimization for low-latency inference.
Integrating AI perception with system-level control.

Mentoring session schedule and details

PS#	Date	Time	Meeting Link
2	9th Feb	4:30 – 5 PM	Zoom link Meeting ID: 942 3402 8311 Passcode: 706803

Problem Statement 3 Real-Time Road Anomaly Detection from Dashcam Footage on Raspberry Pi

Winning Team

Team	VigiaSENSE
Institution	National Institute of Technology, Rourkela
Team Members	Tom Mathew, Ben Biju, Shreeram Balasubramanian

Objective

Build an edge AI application on Raspberry Pi that processes dashcam footage in real-time to detect and log road anomalies such as potholes and unexpected obstacles.

Project Description

Students will choose a lightweight object detector (e.g., MobileNet-SSD, YOLOv5s), convert it to an edge-optimized format (TensorFlow Lite / ONNX Runtime / ExecuTorch), and integrate it with an OpenCV video pipeline. Detected anomalies should trigger timestamped logs or saved clips.

Key Requirements

Hardware:
- Raspberry Pi 5 or 4.
- Raspberry Pi Camera Module v2 or USB webcam.
- High-write-speed microSD card.
- Where possible, aim to use the CPU without additional accelerators/hats. Solutions that are well-optimised through use of Quantisation, KleidiAI, and appropriate model selection - and therefore able to run entirely on CPU - are of great interest.
Software:
- Raspberry Pi OS.
- Python, OpenCV.
- TensorFlow Lite / ONNX Runtime / ExecuTorch with a pre-trained, quantized detection model.

Performance Targets

≥5 FPS near-real-time inference.
High precision to reduce false positives in logging.
Robust under varying lighting conditions.

Deliverables

Source code for video processing and inference pipeline.
Optimized deployed model file (.tflite / .onnx).
Demo video with anomaly detection on sample footage.
Report on model choice, optimization and performance.

Learning Outcomes

Optimizing and deploying neural networks for edge video analytics.
Experience with embedded vision pipelines.
Understanding accuracy vs speed vs compute trade-offs on Arm platforms.

Mentoring session schedule and details

PS#	Date	Time	Meeting Link
3	9th Feb	3:30 – 4 PM	Zoom link Meeting ID: 957 4790 4145 Passcode: 521992

Problem Statement 4 Real-Time On-Device Speech-to-Speech Translation using SME2 and/or NEON on Arm CPU

Winning Team

Team	BhashaBridge
Institution	Chennai Institute of Technology, Malayambakkam
Team Members	V Paresh Kumar, Vishnu Vardhan KS, Yugawathi E

Objective

Build a fully local, real-time speech-to-speech translation system optimized for Arm-based CPUs, leveraging SME2 where available (preferred) or NEON or an onboard NPU otherwise. The system must perform speech recognition, LLM-based translation or semantic rewriting, and speech synthesis entirely on-device, meeting mobile latency, power, and thermal constraints.

Project Description

Students will design and deploy a real-time, on-device speech-to-speech translation pipeline running on a smartphone with an Arm-powered CPU (preferably SME2-enabled devices such as OPPO Find X9 or vivo X300).

The system captures continuous spoken audio in Language A, performs:

On-device speech-to-text (STT),
LLM-based translation or semantic rewriting, and
Text-to-speech (TTS) synthesis,

to produce natural, fluent spoken output in Language B. All inference must run locally with no cloud dependency, demonstrating efficient use of Arm CPU acceleration and mobile-friendly optimizations. To see all SME2-enabled devices, and for resources to get started, see this related Arm Developer Labs project. Edge AI on Mobile using SME2

Key Requirements

Hardware:
- Arm-based smartphone CPU
- SME2-enabled device preferred; otherwise utilise an Arm-based CPU and NEON instructions or optional onboard NPU
- Microphone and audio output (speaker or headphones)
- Where possible, aim to use the CPU (leveraging SME2 if available) without using an onboard NPU. Solutions that are well-optimised through use of Quantisation, KleidiAI, and appropriate model selection - and therefore able to run entirely on CPU - are of great interest.
- No cloud inference permitted
Software:
- Speech-to-Text (STT):
  - Small-footprint on-device ASR model
  - Examples: Whisper-tiny (int8), Wav2Vec2-lite, Vosk
- LLM-Based Translation / Rewrite:
  - Compact on-device LLM
  - Examples: Phi-2 (int4/int8), Gemma-2B (int4)
  - Supports either direct translation or semantic rewriting for fluency
- Text-to-Speech (TTS):
  - Low-latency neural acoustic model and vocoder
  - Examples: FastSpeech2 + HiFiGAN, VITS-lite

Performance Targets

Near real-time end-to-end latency suitable for conversational use
Efficient on-device inference using quantized and optimized models
Energy-aware operation to maintain acceptable thermal and power behavior on mobile SoCs
Intelligible, natural-sounding synthesized speech output with minimal delay

Deliverables

Fully functional on-device speech-to-speech translation pipeline
Demonstration running on an Arm-based smartphone
Performance evaluation including latency, CPU utilization, and power considerations
Documentation describing model choices, optimizations (SME2/NEON), and system architecture

Learning Outcomes

Understanding of end-to-end speech-to-speech AI pipelines
Hands-on experience optimizing AI workloads for Arm CPUs
Practical knowledge of model quantization and mobile inference constraints
Insight into energy-efficient, low-latency system design for edge AI
Exposure to SME2 and NEON optimization strategies on modern Arm platforms

Mentoring session schedule and details

PS#	Date	Time	Meeting Link
4	9th Feb	4 – 4:30 PM	Zoom link Meeting ID: 922 9571 9466 Passcode: 886929

Problem Statement 5 Real-Time Object Detection Using Hardware-Accelerated CNN on Xilinx Zynq FPGA with Arm Processor

Winning Team

Team	Ad Astra
Institution	B V Raju Institute of Technology, Narsapur
Team Members	Cherala Rohan, Karthik Pakala

Objective

Design and implement a hardware-accelerated CNN inference system on a Xilinx Zynq SoC, leveraging FPGA fabric to achieve real-time object detection or image classification, and quantitatively demonstrate performance improvements over a CPU-only implementation.

Project Description

This project focuses on accelerating edge AI workloads on embedded platforms using hardware/software co-design. Students will implement a lightweight convolutional neural network (CNN) for object detection or image classification on a Xilinx Zynq SoC, which integrates an Arm processor with FPGA fabric.

The system partitions functionality between the Arm core and FPGA:

The Arm core handles image capture, preprocessing, control logic, and post-processing.
The FPGA fabric accelerates compute-intensive CNN operations such as convolution, activation, and pooling using Vitis HLS or Vivado.

The final system will perform real-time inference using either a live camera feed or a standard dataset, with detailed performance comparison against a software-only CPU implementation.

Key Requirements

Hardware:
- Xilinx Zynq-based development board
- Examples: Zynq-7000, ZCU104, ZedBoard
- Camera input (USB or onboard) or stored image dataset
- Display output or serial console for results
Software:
- CNN Models:
  - Lightweight models such as Tiny-YOLO, MobileNet, or a custom 3-layer CNN
- FPGA Design:
  - Vitis HLS or Vivado for CNN accelerator implementation
  - Verilog or HLS C++ for hardware modules
- Embedded Software:
  - Vitis / SDSoC for HW/SW co-design
  - Optional PetaLinux
  - OpenCV for image capture and preprocessing
  - C++ or Python for control logic and system integration

Performance Targets

Real-time or near real-time inference on embedded hardware
Minimum 2× speedup compared to software-only CNN execution on Arm CPU
Measurable improvements in:
- Latency
- Throughput
- Power efficiency
- Efficient use of FPGA resources (LUTs, BRAM, DSPs)

Deliverables

Working FPGA-accelerated CNN prototype performing object detection or image classification
Hardware/software co-design implementation running on a Zynq platform
Performance comparison between:
- CPU-only implementation
- Hardware-accelerated implementation
Documentation covering:
- System architecture
- Design partitioning decisions
- Performance analysis (latency, throughput, resource usage, power)
Live demo or recorded demonstration of real-time inference

Learning Outcomes

Understanding of embedded edge AI and CNN inference pipelines
Practical experience with FPGA-based acceleration using HLS
Skills in Arm–FPGA hardware/software co-design
Performance analysis and optimization of embedded systems
Insight into trade-offs between flexibility, performance, and power in heterogeneous SoCs

Mentoring session schedule and details

PS#	Date	Time	Meeting Link
5	9th Feb	5 – 5:30 PM	Zoom link Meeting ID: 990 8679 9647 Passcode: 584639

Registration Closed

Objective

Eligibility Criteria

Challenge Guidelines & Terms

Detailed Timeline

Support & Queries

Frequently Asked Questions (FAQ)

Frequently Asked Questions

Finalist Announcement

Project Problem Statements

Winning Team

Objective

Project Description

Key Requirements

Performance Targets

Deliverables

Learning Outcomes

Mentoring session schedule and details

Winning Team

Objective

Project Description

Key Requirements

Performance Targets

Deliverables

Learning Outcomes

Mentoring session schedule and details

Winning Team

Objective

Project Description

Key Requirements

Performance Targets

Deliverables

Learning Outcomes

Mentoring session schedule and details

Winning Team

Objective

Project Description

Key Requirements

Performance Targets

Deliverables

Learning Outcomes

Mentoring session schedule and details

Winning Team

Objective

Project Description

Key Requirements

Performance Targets

Deliverables

Learning Outcomes

Mentoring session schedule and details

Thank You!